/*
*	Reg_Files Test file
*
*
*/

`include"../CPU/Reg_Files.v"

module Reg_Files_Test;
	reg[31:0] writeData;
	wire[31:0] RD1,RD2;
	reg[4:0] A1,A2,A3;
	reg clock,WE3;
	initial begin
		clock = 0;
		WE3 = 1;
	end
	initial begin
		writeData = 1;
		A3 = 1;
		A1 = 1;
		A2 = 2;
		clock = 1;
		#1 clock = 0;
		writeData = 2;
		A3 = 2;
		#1 clock = 1;
		clock = 0;
		
		
	end
	
	initial begin
		$monitor("Time = %0d,clock is %b,RD1 = %d, RD2 = %d",$time,clock,RD1,RD2);
	end
		
	Reg_Files myReg(clock,A1,A2,A3,writeData,WE3,RD1,RD2);
	
endmodule
